Design, Analysis and Test of Logic Circuits Under Uncertainty

Design, Analysis and Test of Logic Circuits under Uncertainty bySmita Krishnaswamy Co-Chairs: John P. Hayes and Igor L. Markov Integrated circuits (ICs) are increasingly susceptible to uncertainty caused by softerrors, inherently probabilistic devices, and manufacturing variability. As device tech-nologies scale, these effects become detrimental to circuit reliability. In order to addressthis, we develop methods for analyzing, designing, and testing circuits subject to prob-abilistic effects. Our main contributions are: 1) a fast, soft-error rate (SER) analyzerthat uses functional-simulation signatures to capture error effects, 2) novel design tech-niques that improve reliability using little area and performance overhead, 3) a matrix-based reliability-analysis framework that captures many types of probabilistic faults, and4) test-generation/compaction methods aimed at probabilistic faults in logic circuits.SER analysis must account for the three main error-masking mechanisms in ICs: logic,timing, and electrical masking. We relate logic masking to node testability of the circuitand utilize functional-simulation signatures, i.e., partial truth tables, to efficiently compute estability (signal probability and observability). To account for timing masking, we com-pute error-latching windows (ELWs) from timing analysis information. Electrical maskingis incorporated into our estimates through derating factors for gate error probabilities. TheSER of a circuit is computed by combining the effects of all three masking mechanismswithin our SER analyzer called AnSER.Using AnSER, we develop several low-overhead techniques that increase reliability,including: 1) an SER-aware design method that uses redundancy already present withinthe circuit, 2) a technique that resynthesizes small windows of logic to improve area andreliability, and 3) a post-placement gate-relocation technique that increases timing mask-ing by decreasing ELWs.We develop the probabilistic transfer matrix (PTM) modeling framework to analyzeeffects beyond soft errors. PTMs are compressed into algebraic decision diagrams (ADDs)to improve computational efficiency. Several ADD algorithms are developed to extractreliability and error susceptibility information from PTMs representing circuits.We propose new algorithms for circuit testing under probabilistic faults, which requirea reformulation of existing test techniques. For instance, a test vector may need to berepeated many times to detect a fault. Also, different vectors detect the same fault withdifferent probabilities. We develop test generation methods that account for these differ-ences, and integer linear programming (ILP) formulations to optimize test sets.